The present invention relates to a logic circuit and, more particularly, to technology which is effective especially when applied to the so-called "SPL (as abbreviated from Super Push-pull Logic) circuit" to be packaged in a high speed logic integrated circuit device constituting a high speed computer.
A known type of circuit, referred to as an NTL (as abbreviated from Non-Threshold Logic) circuit, includes a phase division circuit (a phase splitter circuit) made responsive to an input signal and an output emitter follower circuit for transmitting the inverted output signal of the phase division circuit.
We developed the so-called "SPL (abbreviated from Super Push-pull Logic) circuit", as an NTL circuit which had its output unit replaced by an active pull-down circuit. This was filed as the patent application bearing Ser. No. 07/330,461 on Mar. 30, 1989 (now U.S. Pat. No. 4,999,520).
This previously developed SPL circuit is equipped, as exemplified in FIG. 9, with a phase division circuit which includes: an input transistor (a phase splitter transistor) T1 made receptive of an input signal SI; and a collector resistor R5 and an emitter resistor R4 connected, respectively, between the ground potential of the circuit and the collector of the input transistor T1 and between the emitter of the input transistor T1 and the supply voltage of the circuit. The inverter output signal of the phase division circuit, i.e., the collector potential of the input transistor T1, is fed to the base of an output transistor T3. The non-inverted output signal of the phase division circuit, i.e., the emitter potential of the input transistor T1, is fed to the base of a pull-down transistor T4 through a differentiation circuit composed of a capacitor C1 and a resistor R1. This pull-down transistor T4 has its base coupled to receive a predetermined bias voltage VB which is established immediately before the bias circuit is turned on. This bias voltage can be provided via the bias transistor T2. Thus, the pull-down transistor T4 acts as an active load for the output transistor T3 an constitutes an active pull-down circuit together with the capacitor C1 and the resistor R1. As a result, the SPL circuit has its sensitivity enhanced and its operations speeded up.
Prior to the present invention, we have developed the SPL circuit which is improved, as shown in FIG. 7, over the aforementioned SPL circuit of FIG. 9. Specifically in FIG. 7, the SPL circuit includes: a P-channel MOSFET Q1 connected between the ground potential of the circuit and the collector of the input transistor T1 and having its gate made receptive of the input signal SI; and a diode D1 connected in parallel with the MOSFET Q1. The MOSFET Q1 and diode D1 act not only as variable impedance means for the input transistor T1. The MOSFET Q1 also acts as active pull-up means for speeding up the rise of an output signal SO. The diode D1 acts as level setting means for setting the low level of the output signal SO. As a result, the SPL circuit has its power consumption reduced while having its operations speeded up and stabilized.